The integration of multiple digital signal processing (DSP) blocks, wideband digital-to-analog converters (DACs), and wideband analog-to-digital converters (ADCs) within a single monolithic chip is now enabling the offload of power hungry FPGA resources to allow for smaller footprint, lower power, increased channel count platforms that can sample at higher rates than previously achievable. Along with this new capability comes novel multichip synchronization (MCS) algorithms within these integrated circuits (ICs), which allow users to achieve a known (deterministic) phase for all channels when powering the system or otherwise making software modifications to the system. This deterministic phase therefore simplifies the broader system-level calibration algorithms needed to achieve the synchronization of all channels at the output or input to the front-end networks attached to these ICs. This article presents experimental results that demonstrate this MCS capability while using a 16-channel receiver/transmitter platform consisting of multiple digitizer ICs, clock sources, and digital interfaces.


Related Content

RF Technical Articles
Next-Generation Military Communications Challenges
The next generation of MILCOM platforms will need to leverage more modern communication technologies that have been developed to enable commercial platforms such as cell phones and Wi-Fi.
October 11, 2022

RF Technical Articles
A Review of Wideband RF Receiver Architecture Options
This article compares the benefits and challenges of three common receiver architectures: a heterodyne receiver, a direct sampling receiver.
September 12, 2022

Radar Application
Combining the Best of Both Worlds: True Time Delays and Phase Shifters
This article reviews the strengths and weaknesses of two electronic beamforming techniques: phase shifters (PSs) and true time delays (TTDs).
September 5, 2022